Join Dr. Devendra Sadana of the IBM Thomas J. Watson Research Center at 4 p.m. Thursday, April 16, in 1002 ECE Building for a presentation on High Performance CMOS.
Abstract:
Major challenges exist to scale performance in 10 nm and beyond CMOS due to shrinking device footprint and disproportionately reduced volume available for performance enhancing elements. In particular, application of stressors, such as e-SiGe, e-Si:C, and dielectric layers that allowed performance scaling of CMOS since 90 nm node is no longer sufficient to meet the required performance target of future CMOS. This talk will discuss materials and process options for future CMOS.
Bio:
Devendra Sadana is a Distinguished Engineer and the manager of the Advanced Substrate Research Group at IBM TJ Watson Research Center, Yorktown Heights. He has been at IBM Research for over 28 years. Prior to IBM, he worked at Oxford University, UC Berkeley, Microelectronics Center of North Carolina, and Philips Research Labs. His research spans a wide spectrum of advanced materials targeted for a variety of products including Si CMOS, Si and III-V PV, phtotonics, and flexible electronics. He has published over 200 papers in journals/conference proceedings and is a co-inventor of over 400 issued/submitted patents. He is a fellow of SPIE.
